(1) Field of the Invention
The invention relates to a multi-chip package, and more particularly to a stacked multi-chip package.
(2) Description of the Prior Art
With the development of wireless communication network, the demand of portable communication apparatus, such as cell phones and personal digital assistants (PDA), is gradually increase. Meanwhile, the progress in the communication technology also promotes various types of specific services, such as digital music download, on-line chat room, on-line games, and messages delivery, provided on the cell phone. However, these services also lead to a great demand of large data transmission capacity. As a result, the requirement of memory chip with better performance facilitating the cell phone is becoming urgent.
For fabricating such memory chip, a variety of manufacturing technologies focusing on increasing memory cell density and reducing power consumption are regarded. However, such methods are quite costly and risky. By contrast, Stacked Multi-Chip Package (ST-MCP) technology, which is applied based on the existing chip manufacturing technologies but reduces the size of the chip package and the power consumption, is a much better solution in present.
FIG. 1 shows a cross-sectional view depicting a traditional stacked multi-chip package 100. The stacked multi-chip package 100 includes a first circuit board 110, a second circuit board 120, a third circuit board 130, a first chip 140, and a second chip 150. The first chip 140 is placed on the first circuit board 110 and electrically connected with the first circuit board 110. The second chip 150 is placed on the second circuit board 120 and electrically connected with the second circuit board 120. The third circuit board 130 is sandwiched between the first circuit board 110 and the second circuit board 120 and has an opening 132 aligning with the first chip 140 for offering a heat dissipation space A right above the first chip 140.
For electrically connecting the three circuit boards, a plurality of solder balls 160 are provided on the both surfaces of the third circuit board 130 to connect with the first circuit board 110 and the second circuit board 120. By the way, the signals from the second chip 150 may pass through the second circuit board 120 and the third circuit board 130 to reach the first circuit board 110, or even transmitted downward to a main board (not shown).
However, the traditional stacked multi-chip package 100 has the following drawbacks. Firstly, the solder balls 160 sandwiched between the three circuit board 110, 120, and 130 lead to a significant increase in the package thickness and cost. Secondly, the density of the contacts of the traditional stacked multi-chip package 100 is restricted by the pitch P of the adjacent solder balls 160 and is impossible to increase without limitation. Thirdly, the layout of the circuits on the first circuit board 110, the second circuit board 120, and the third circuit board 130 is restricted by the arrangement of the solder balls 160, and may lead to an inconvenience for circuit design. Fourthly, the third circuit board 130 sandwiched between the first circuit board 110 and the second circuit board 120 has the opening 132 to offer the heat dissipation space A for improving heat dissipation rate of the first chip 140. However, an additional third circuit board 130 leads to a tremendous increase in package thickness, meanwhile the package cost.
With the increasing demand of stacked multi-chip packages, how to modify the traditional stacked multi-chip package to achieve the goals of high heat dissipation efficiency and small package size has become a major issue of package technologies nowadays.